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cyil1sm1300aa lupa-1300 1.3 mpxl high speed cmos image sensor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05711 rev. *d revised september 21, 2009 preamble overview this document describes the in terfacing and the driving of the image sensor lupa-1300, which is a 1280 by 1024 cmos pixel array working at 450 frames/sec. the sensor is an active pixel sensor with synchronous shutter. the pixel size is 14 * 14 m and the sensor is designed to achieve a fame rate of 450 frames/sec at full resolution. this high frame rate can be achieved by 16 parallel output amplifiers each working at 40 mhz pixel rate. the readout speed can be boosted by means of windowed region of interest (roi) readout. high dynamic range scenes can be captured using the double slope functionality. the sensor uses a 3-wire serial -parallel interface (spi). it is housed in a 145-pin ceramic pga package. in the following sections the different modules of the image sensor are discussed more into detail. this data sheet allows the user to develop a camera-system based on the described timing and interfacing. main features the main features of the image sensor are identified as: sxga resolution: 1280 x 1024 active pixels. 14 m 2 square pixels (based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others)). pixel rate of 40 mhz using 16 parallel outputs. random programmable windowing. dual slope integration possible. 145-pin pga package. peak qe x ff of 15%. optical format: 1,43" (17.9 mm x 14.3 mm). optical dynamic range: 62 db (1330:1) in single slope operation and 80 to100 db in double slope operation. 16 parallel analog output amplifiers. synchronous pipelined shutter. processing is done in a cmos 0.50 m triple metal process. ordering information marketing part number description package cyil1sm1300aa-gdc mono with glass 145-pin pga cyil1sm1300aa-gwc mono without glass [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 2 of 29 specifications general specifications electro-optical characteristics overview table 1. general specifications of the lupa sensor parameter specification remarks pixel architecture 6t-pixel based on the high-fill factor active pixel sensor technology of fillfactory. pixel size 14 m x 14 m the resolution and pixel size results in a 17.9 mm x 14.3 mm optical active area. resolution 1280 x1024 pixel rate 640 mhz using a 20 mhz syst em clock and 16 parallel outputs. shutter type pipelined snapshot shutter full snapshot shutter with variable integration time. full frame rate 450 frames/second frame rate increa se possible with roi read out and/or sub sampling. package pin grid array 145 pins pga pins with 0.46 mm diameter. table 2. electrical-optical specifi cations of the lupa-1300 sensor parameter specification remarks fpn <3% rms <10% p/p. prnu 2% rms half saturation. conversion gain 16 v/electron output signal amplitude 1v unity gain. saturation charge 62.500 e- is more then 60.000 (=1v/16v/e-) due to non-linearity in saturated region. sensitivity 1500 v.m2/w.s average white light. 8.33 v/lx.s visible band only (180 lx = 1 w/m2). 21.43 v/lx.s visible + nir (70 lx = 1 w/m2). fill factor 50% 100%-metal and polycide coverage. peak qe * ff peak sr * ff 15% 0.08 a/w see spectral response curve. mtf x: 67% y: 66% at nyquist. temporal noise 45e- dark environment, measured at t=21 o c. s/n ratio 1330 1330 = 60000:45 = 62 db. spectral sensitivity range 400 - 1000 nm parasitic light sensitivity < 0.5% i.e., sensitivity of t he storage node compared to t he sensitivity of photodiode. power dissipation 900 mwatt typical. output impedance 200-300 typical. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 3 of 29 features and general specifications spectral response curve figure 1. spectral response curve figure 1 shows the spectral response characteristic. the curve is measured directly on the pixels. it includes effects of non-sensitive areas in the pixel, e.g., interconnection lines. the sensor is light sensitive bet ween 400 and 1000 nm. the peak qe * ff is 15% approximately between 500 and 700 nm. table 3. features and general specifications feature specification/description electronic shutter type synchronous pipelined shutter with variable integration time. windowing (roi) programmable via spi. readout sequence progressive scan. extended dynamic range double slope extended dynamic range. x clock 20 mhz (pixel rate of 40 mhz). number of outputs 16. supply voltage vdd image core supply: range from 3v to 6 v. analog supply: nominal 5 v. digital: nominal 5 v. logic levels 5v (digital supply) operational temperature range 0c to 60 c, with degradati on of dark current. package 145-pins pin grid array (pga). 0 0.02 0.04 0.06 0.08 0.1 0.12 400 500 600 700 800 900 1000 wavelength (nm) response (a/w) qe=10% qe=15% qe= 20% lupa -1300 [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 4 of 29 photo-voltaic response curve figure 2. output voltage as function of number of electrons as one can see from figure 2 , the output signal ranges between 0 v to 1.1 v and is linear until around 800 mv. note that the upper part of the curve (near saturation) is actually a logarithmic response. electrical specifications absolute maximum ratings note 1. absolute ratings are those values beyond which damage to the device may occur. table 4. absolute maximum ratings 1 symbol parameter value unit v dc dc supply voltage -0.5 to +7 v v in dc input voltage 0.5 to vdc + 0.5 v v out dc output voltage -0.5 to vdc + 0.5 v i dc current per pin; any single input or output (see table 7 for more exceptions). 50 ma t stg storage temperature range -40 to 100 c t l lead temperature (10 seconds soldering) 300 c [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 5 of 29 recommended operating conditions sensor architecture the image sensor consists of the pixel array, the column readout electronics, x-and y addressing, on-chip drivers, the output amplifiers and some logic. notes 2. all parameters are characterized for dc conditi ons after thermal equilibrium has been established. 3. unused inputs must always be tied to an appropriate logic level, e.g., either vdd or gnd. 4. this device contains circuitry to protect the inputs against dam age due to high static voltages or electric fields; however i t is recommended that normal precautions be taken to avoid application of any voltages higher than the maximum rated voltages to this high impedance circuit. 5. all power supplies should be sufficiently decoupled because spikes and drops in the power supplies will be immediately visibl e in the analog output signals. table 5. recommended operation conditions symbol parameter 2 typical unit vdda power supply column read out module 5 v vdd power supply digital modules 5 v vddr power supply logic for drivers 5 v voo power supply output stages 5 v vres power supply reset drivers 6 v vres_ds power supply multiple slope reset driver 4.5 v vmem_h power supply memory element (high level) 6 v vmem_l power supply memory element (low level) 4.5 v vpix power supply pixel array 4.5 v vstable power supply output stages. decouples noise on the voo supply from the output signal. 5.5 v [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 6 of 29 figure 3. architecture of the lupa sensor figure 3 shows a schematic representation of the image sensor on which the different modules are displayed. the image core is a pixel array of 1280 * 1024 pixels each of 14 *14 m2 in size. the readout is from bottom left to top right. to obtain a frame rate of 450 frames/sec for this resolution, 16 output amplifiers each capable of driving an output capacitance of 10 pf at 40 mhz are placed on the image sensor. the column readout amplifiers bring the pixel data to the output amplifiers. the logic and the x- and y addressing controls the image sensor so that progressive scan and windowing is possible. extra pixel array drivers are foreseen at the top of the image sensor to control the global pixel array signals. pixel architecture the active pixels allow synchronous shutter, i.e., all pixels are illuminated during the same integration time, starting from the same moment in time. after a certain integration time, the pixels are readout sequentially. readout and integration are in parallel, which means that when the image sensor is readout, the integration time for the next frame is ongoing. this feature requires a memory element inside the pixel, which affects the maximum fill factor. a schematic representation of the pixel is given in figure 4 . figure 4. schematic representation of synchronous pixel as used in lupa design x-addressing analog multiplexe r column am p li f iers pixel cor e p ixel output amplifiers imager core spi interface senso r y-addressin g system clock 40 mhz 3 2 1 16 15 14 drivers for the pixel array signals control signals p recharge reset sa mp le row select column out vpix mem note 6. the signals mentioned in figure 4 are the internal signals generated by the internal dr ivers required to have the synchronous shutter feature. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 7 of 29 the photodiode is designed to obtain sensitivity as high as possible for a dynamic range of at least 60db. consequently the photodiode capacitance is 10 ff at the output, resulting in a s/n of more than 60 db as the rms noise level is within the expec- tation of 45 noise electrons. the pixel was specially designed to have a very low parasitic light s ensitivity (<0.5%). the pixels are based on the high-fill factor active pixel sensor technology of fillfactory (us patent no. 6,225,670 and others). column readout amplifiers the column readout amplifiers are the interface between the pixels and the output amplifiers. the pixels in the array are selected line by line and the pixels of the selected line are connected to the column readout amplifiers, which bring the pixel data in the correct format to the output amplifiers. to obtain a high frame rate, the complexity and the number of stages in the column readout amp lifiers must be minimized, so that the power dissipation remains as low as possible, but also to minimize the row blanking time. figure 5 is a schematic repre- sentation of the column readout stru cture. it consists of two parts. the first part is a module that reduces the row blanking time. the second part shifts the signal to the correct level for the output amplifiers and allows multiplexing in the x-direction. from the moment that a new row is selected, the pixel data of that row is placed onto the columns of the pixel array. these columns are long lines and have a large parasitic capacitance. as the pixel is small, it is not possible to match the transistor inside the pixel, which drives th is column. consequently, the first module in the column readout amplifiers must solve the mismatch between the pixel driver and the large column capac- itance. figure 5. schematic representation of column readout structure output amplifiers 16 output amplifiers each capable of working at 40 mhz pixel ra te are placed equidistant on the bottom of the image sensor. the se output amplifiers are required to obtain a frame rate of 450 fr ames/sec. a single output stage, not only to reduce power, but a lso to achieve the required pixel rate is designed. figure 6 is a schematic representation of this module figure 6. schematic representation of single output stage output stage column module 1 : track & hold or reference set method module 2 : signal conditioning and multiplexing x-mux shkol norow sel stabilize power supply vstable in out output stage cload d 10 pf [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 8 of 29 each output stage is designed to dr ive a load of 10 pf at a pixel rate of 40 mhz. the load in the output stage determines this pixel rate. in case the load capacitance is less than 10 pf, the load in the output stage can increase, resulting in less power dissipation of the output stages and conse quently of the whole sensor. additionally, decreasing the load of the output stage allows having more current available for the output stage to charge or discharge the load capacitance to obtain a higher pixel rate. to avoid variations on the supply voltage to be seen on the output signal, a special module to stabilize the power supply is required. this module that requires an additional supply voltage (vstable) allows variation on the supply voltage voo without being seen on the output signal. one can also choose to have a passive load of chip instead of the active output stage load. this deteriorates the linearity of the output stages, but decreases the power dissipation, as the dissi- pation in the load is external. frame rate and windowing frame rate calculation the frame period of the lupa-13 00 sensor can be calculated as follows: frame period = fot + (nr.lns* (rbt + pixel period * nr. pxs/16) with: fot: frame overhead time = 1 us. nr. lns: number of lines read out each frame (y). nr. pxs: number of pixels read out each line (x). rbt: row blanking time = 200 ns (nominal; can be further reduced). pixel period: clock_x period/2 ( both rising and falling edge are active edges). - example 1 read out of the full resolution at nominal speed (40 mhz pixel rate): frame period = 5 us + (1024 * (200 ns + 25 ns * 1280/16) = 2.25 ms => 444 fps. - example 2 read out of 800x600 at nominal speed (40 mhz pixel rate): frame period = 5 us + (600 * (200 ns + 25 ns * 800/16) = 871 us => 1148 fps. - example 3 read out of 640x480 at nominal speed (40 mhz pixel rate): frame period = 5 us + (480 * (200 ns + 25 ns * 640/16) = 577 us => 1733 fps. - example 4 read out of the full resolution at nominal speed (40 mhz pixel rate) with reduced overhead time: frame period = 5 us + (1024 * (100 ns + 25 ns * 1280/16) = 2.15 ms => 465 fps. x-y addressing and windowing the pixel array is readout by means of programmable x and y shift registers. the pixel array is scanned line-by-line and column-by-column. the starting point in x and y is defined individually for each register and is determined by the address downloaded by the serial-parallel interface (spi). both registers work in the same way. a sync pul se that sets the address pointer to the starting address of each register, initializes them. a clock pulse for the x- and y-shift regist er shifts the pointer individually and makes sure that the sequential selection of the lines and columns is correct. temperature refe rence circuits temperature diode the most commonly used temperature measurement is monitoring of the junction voltage of a diode, therefore we also added a temperature diode to m easure the temperature of the silicon die. this diode junction voltage is generated by a "small", forward biased, constant current flow (in between 10 and 100 a). this junction voltage has a nearly linear relationship with the temperature of the die with a typical sensitivity of about 430c per volt (2.3 mv per c ) for silicon junctions. temperature module on the same image sensor we have foreseen a module to verify the temperature on chip and the variation of the output voltage (dark level of the pixel array) due to a temperature variation. this module contains a copy of the complete signal path, including a blind pixel, the column amplif iers and an output stage. it dc response may serve a temperature calibration for the real signal. the temperature functionality is given in figure 7 . between room temperature and 60 o c we see a voltage variation of about 0.5 mv. due to different applied supply vo ltages, as there are: vreset, vmem, vpix an offset between th e output voltage of the temper- ature sensor and the output of a black signal of the pixel array can occur. depending on the working conditions of the image sensor one can fine-tune the tem perature module with its voltage supply. in case one has a 6v signal for reset and a 4-6v signal for vmem, a supply voltage of 5.5v for the temperature sensor will result in a closer match between this temperature sensor and the black level of the image sensor. changing the supply voltage of the temperature sensor results only in a shift of the output voltage therefore the supply voltage of the temperature module can be tuned to make the output of the module equal to the dark signal of the pixel array at a certain working temperature. note 7. the lupa-1300 is designed to drive a capacitive load, not a resistive. when one wants to transport the output signals over lo ng distances (more than 1 inch), make sure to place buffers on the outputs with high input imp edances (preferably >1mohms). this is necessary because the output impedance of the lupa-1300 is between 200-300 typically. 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cyil1sm1300aa document number: 38-05711 rev. *d page 9 of 29 figure 7. output voltage of temperature module versus temperature synchronous shutter in a synchronous (snapshot) shutter light integration takes plac e on all pixels in parallel, although subsequent readout is seq uential. figure 8. synchronous shutter operation figure 8 shows the integration and read out sequence for the synchronous shutter. all pixels are light sensitive at the same period of time. the whole pixel core is reset simultaneously and after the integration time all pixel values are sampled together on the storage node inside each pixel. the pixel core is readout line by line after integration. vsupply (v) 5 5.5 6 6.1 6.2 6.3 6.4 6.5 vout at 21 o c 0.58 0.8 1.03 1.07 1.12 1.17 1.22 1.27 0.99 1.01 1.03 1.05 1.07 1.09 1.11 1.13 25 35 45 55 65 75 te m p e r a t u r e ( c ) vout (v) 6 6.1 6.2 time axis line number integration time burst readout time common reset common sample&hold flash could occur here note 8. note that the integration and readout cycle can occur in parallel. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 10 of 29 figure 9. integration and readout in parallel the control of the readout of t he frame and of the integration time are independent of each other with the only exception that the end of the integration time from frame i+1 is the beginning of the readout of frame i+1. non-destructive readout (ndr) the sensor can also be read out in a non-destructive way. after a pixel is initially reset, it can be read multiple times, with out resetting. the initial reset level and all intermediate signals can be record ed. high light levels will saturate the pixels quickly, but a useful signal is obtained from the early samples. for low light levels, one has to use the later or latest samples. figure 10. principle of non-destructive readout essentially an active pixel array is read multiple times, and reset only once. the external system intelligence takes care of the interpretation of the data. ta b l e 6 summarizes the advantages and disadvantages of non-destructive readout. operation and signaling one can distinguish the different signals into different groups: power supplies and grounds biasing and analog signals pixel array signals digital signals test signals power supplies and grounds every module on chip, as there are: column readout, output stages, digital modules, drivers, has its own power supply and ground. off chip the grounds can be combined, but not all power supplies may be combined. th is results in several power supplies, but is required to r educe electrical crosstalk and to improve shielding. on chip we have the ground lines also separately for every module to improve shielding and electrical crosstalk between them. the only special ground is "gnd_res", which can be used to remove the blooming if any and which can improve optical crosstalk. an overview of the supplies is given in table 7 . the power supplies related to the pixel array signals are described in the paragraph concerning the pixel array signals. i ntegration i + 2 r ead frame i + 1 i ntegration i + 1 r ead frame i time table 6. advantages and disadvantages of non-destructive readout advantages disadvantages low noise ? as it is true cds. system memory required to record the reset level and the intermediate samples. high sensitivity ? as the conversion capacitance is kept rather low. requires multiples readings of each pixel, thus higher data throughput. high dynamic range ? as the results include signal for short and long integrations times. requires system level digital calculations. note 9. normal application does not require this gnd_res and it can be connected to ground. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 11 of 29 the maximum currents mentioned in table 7 are peak currents. the power supplies need to be able to deliver these currents especially the maximum supply current for vpix. it is important to notice that we don't do any power supply filt ering on chip and that noise on these power supplies can contri bute immediately to the noise on the signal. especially the voltage supplies vpix and vdda are important to be well noise free. with respect to the power supply voo, a special decoupling is used, for which an additional power supply vstable is required. figure 11a. schematic of typical decoupling of power supply (source current) figure 11b. schematic of typical decoupling of power supply (source current) table 7. power supplies used in the lupa design name max current typ. max description vdda 50 ma 5v power supply column readout module vdd 20 ma 5v power supply digital modules voo 85 ma 5v power supply output stages vstable 6 ma 5.5v 6v power supply output stages. decouples noise on the voo supply from the output signal. vpix 200 ma 4.5v 6v power supply pixel array vddr 20 ma 5v power supply logic for drivers vres 50 ma 6v power supply to reset the pixels vmemh 50 ma 6v power supply for high dc level vmem vmeml 50 ma 4.5v power supply for low dc level vmem notes 10. at start up the vpix supply draws a very high current (> 3 00 ma) which has to be limited (max. 200 ma) otherwise the bond wi res of the particular supply will be destroyed. one should make sure that the vpix power supply limi ts the current draw to the vpix sensor supply pins to max. 20 0 ma. when the bond wires of vpix are destroyed the sensor isn't operating no rmally and will not meet the described specifications. 11. vmeml must sink a current, not source it. all power supplies sh ould be decoupled very close to the sensor pin (typical 100 n f to filter high frequency dips and 10 microf to filter slow dips). a typical decoupling circuit is shown in figure 11 . vres_ds must be able to sink and source current. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 12 of 29 biasing and analog signals besides the biasing signals, the only analog signals are the output signals out1 - out16. each output signal is analog with res pect to the voltage level, but is discrete in time. this means that on the speed of clock_x, the outputs change to a different level, d epending on the illumination of the corresponding pixels. the biasing signals determine the speed and power dissipation of the different modules on chip. these biasing signals have to b e connected trough a resistor to ground or power supply and should be decoupled with a capacitor. if the sensor is working proper ly, each of the biasing signals will have a dc-voltage depending on the resistor value and on the internal circuitry. these dc-volt ages can be used to check the operation of the image sensor. ta b l e 8 gives the different biasing signals , the way they should be connected, and the expected dc-voltage. due to small process variations, th ese dc-voltages change from chip to chip and 10% variation is possible. each resistor controls the speed and power dissipation of the corresponding module, as this resistor determines the current req uired to charge and/or discharge internal nodes inside the module. a decoupling with a small capacitor is advisable to reduce the hf noise onto the analog signals. only the capacitor on the pre_ load signal can be omitted. pixel array signals figure 4 is a schematic representation of the pixel as used in the lupa design. the applied signals to this pixel are: reset, sample, precharge, vmemory, row select and vpix. these are internal ge nerated signals derived by on-chip drivers from external applied signals. consequently it is im portant to understand the relation between both internal and external signals and to understand t he operation of the pixel. the timing of the pixel is given in figure 12 in which only the internal signals are given. figure 12. internal timing of the pixel at the end of the integration time, the information on the photodiode node needs to be sampled and stored onto the pixel memory , required to allow synchronous shutter. to do this, we need the signals "precharge" and "sample". "precharge" resets the pixel memory and "sample" places the pixel information onto the pixel memory. once this information stored, the readout of the pixel memorie s can start in parallel with a new integration time. an additional signal "vmem" is needed to obtain a larger output swing. table 8. overview of biasing signals signal comment expected dc level pre_load connect with 10 k to vdda and capacitor of 100 nf to gnd 2.0v col_load connect with 2 m to vdda and capacitor of 100 nf to gnd 0.9v psf_load connect with 240 k to gnd and capacitor of 100 nf to vdda 3.7v nsf_load connect with 100 k to vdda and capacitor of 100 nf to gnd 1.3v load_out connect with 27 k to voo and capacitor of 100 nf to gnd 1.6v decx_load connect with 27 k to gnd and capacitor of 100 nf to vdd 2.8v decy_load connect with 27 k to gnd and capacitor of 100 nf to vdd 2.8v [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 13 of 29 except from vpix power supply, drivers ge nerate the other pixel signals on chip. the external signals to obtain the required pu lses consist of two groups. one is t he group of digital signals to indicate when the pulse must occur and the other group is dc-supp ly lines indicating the levels of the pulses. table 9 summarizes the relation between the internal and external pixel array signals. the precharge and sample signals are the most straightforward signals. the internal signal vmem ory is a signal that switches between a low voltage (3.5 - 5.5v) and a high voltage (5-6v). the signal mem_hl controls the applied level and the power supply lines vmem_l and vmem_h determine the low and high dc-levels. the reset signal is due to the dual slope technique a little more complex. in case the dual slope is not used, the reset signal is straightforward generated from the external reset pulse. in this case the supply voltage vres determines the level to which the pixel is resetted. in case the dual slope operation is desired, one needs to give a second pulse to a lower reset level during integration. this can be done by the control signal reset_ds and by the power supply vres_ds that defines the level to which the pixel has to be resetted. if a pulse is given on the reset_ds signal, a second pulse on the internal reset line is generated to a lower level, determined by the supply vres_ds. if no reset_ds pulse is given, the dual slope technique is not implemented. note that reset is dominant ov er reset_ds, which means that the high voltage level will be applied for reset, if both pulses occur at the same time. the external control signals should be capable of driving input capacitance of about 20 pf. digital signals the following digital signals control the readout of image sensor: sync_y: starts the readout of the frame or window at the address defined by the y-address register. this pulse synchro- nizes the y-address register: active high. this signal is at the same time the end of the frame or window and determines the window width. clock_y: clock of the y-register. on the rising edge of this clock, the next line is selected. sync_x: starts the readout of the selected line at the address defined by the x-address register . this pulse synchronizes the x-address register: active high. this signal is at the same time the end of the line and determines the window length. address: the x- and y-address is downloaded serial through this signal. clock_spi: clock of the serial parallel interface. this clock downloads the address into the spi register. load_addr: when the spi register is downloaded with the desired address, the signal load_addr signal loads the x-and y-address into their address regist er as starting point of the window of interest. sh_col: control signal of the column readout. is only used in sample & hold mode (see ?timing? on page 14). norow_sel: control signal of the column readout. is only used in norow_sel mode (see ?timing? on page 14). pre_col: control signal of the column readout to reduce row blanking time sel_active: activates the active load on chip for the output amplifiers. if not used, a passive load can be used or one can use this signal to put the output stages in standby mode eos_x: end of scan signal: an output signal, indicating when end of line is reached. is no t generated when doing windowing eos_y: end of scan signal: is an output signal, indicating when the end of the frame is reached. is not generated when doing windowing. all digital signals are buffered and filtered on chip to remove spikes and achieve required on-chip driving speed. applied digital signals should be capable of driving 20 pf input capaci- tance. test signals some test signals are required to evaluate the optical perfor- mance of the image sensor. other test signals allow us to test internal modules in the image sensor and some test signals will give us information concerning temperature and influence of the temperature on the black level. evaluation on optical performance (spectral response, fill factor): array_diode full_diode evaluation of the output stages: black dc_black evaluation of the x and y -shift registers: eos_x eos_y indication of the temperature and influence on the black level: temp_diode_n temp_diode_p table 9. overview of internal and external pixel array signals internal signal vlow vhigh external control signal low dc level high dc level precharge 0 5v precharge gnd vddr sample 0 5v sample gnd vddr reset 0v 4 - 6v reset & reset_ds gnd_res vres & vres_ds vmemory 4.5v 6v mem_hl vmem_l vmem_h [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 14 of 29 timing timing of the pixel array the timing of the image sensor can be divided in two major parts. the first part of the timing is related with the timing of the pixel array. this implies the control of the in tegration time, the synchronous shutter oper ation, and the sampling of the pixel infor mation onto the memory element inside each pixel. the signa ls needed for this control are described earlier and figure 12 shows the timing of the internal signals. figure 13 should make the timing of the external signals clear. figure 13. timing of pixel array. all extern al signals are digital si gnals between 0 and 5v. reset_ds only required in ca se dual slope is desired. the timing of the pixel array is straightforward. before the frame is read, the information on the photodiode needs to be stored onto the memory element inside the pixels. this is done by means of the signals vmemory, precharge and sample. precharge sets the memory element to a reference level and sample stores the photodiode information onto the memory element. vmemory pumps up this value to reduce the loss of signal in the pixel and this signal must be the envelop of precharge and sample. after vmemory is high again, the readout of the pixel array can st art. the frame blanking time or frame overhead time is thus the ti me that vmemory is low, which is about 5 sec. once the readout starts, the photodiodes can all be initialised by reset for the next integration time. the duration of the reset pulse indicates the integration time for the next frame. the longer this duration, the shorter the integration time becomes. maximum integration time is thus the time it takes to readout the frame, minus the mini mum pulse for reset, which is preferred not to be less than 10 sec. the minimal integration time is the minimal time between the falling edge of reset and the rising edge of sample. keeping the slow fall times of the corre- sponding internal generated signa ls, a minimal integration time is about 2 sec. an additional reset pulse can be given during integration by reset_ds to implement the double slope integration mode. readout of pixel array once the photodiode information is stored into the memory element in each pixel, the total pixel array of 1280 * 1024 needs to be readout in less than 2 msec (2 msec - frame overhead time = 1995 sec). additionally, it is possible that only a part of the whole frame is read out. this is controlled by the starting address that has to be downloaded and from the end address, which is controlled by the synchronisation pulses in x- and y direction. the readout itself is straightforw ard. line by line is selected by means of a sync-pulse and by means of a clock_y signal. once a new line selected, it takes a while (row blanking time) before the information of that line is stable. after this row blanking time the data is multiplexed in blocks of 16 to the output amplifiers. a sync-pulse and a clock pulse in the x-direction do this multi- plexing. figure 14 shows the y-address timing. the top curves are the selection signals of the pixels, which are sequentially active, starting by the sync pulse. the next line is selected on the rising edge of clock_y. it is important that the sync_y pulse covers 1 rising edge of the clock_y signal. otherwise the synchronization will not work properly. table 10. typical timings of pixel array symbol name value a mem_hl > 5 sec b mem_hl -precharge > 200 nsec c precharge > 500 nsec d sample > 3.9 sec e precharge-sample > 400 nsec f integration time > 2 sec [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 15 of 29 figure 14. timing of y shift register the first selected line after a sync_y pulse is the line defined by the y-address in the y-address register. every select line is in principle 1 clock period long, except for the first select line. the first select line goes high as soon as a sync_y pulse occurs together with a rising edge of clock_y. on the next rising edge of clock_y, the next ro w is selected, unless sy nc_y is still active. in figure 15 , a short sync_y pulse makes sure that the first row is selected during 1 period of clock_y. once a line is selected, it needs to stabilize first of all, which is called the row blanking time, and secondly the pixels need to be read out. figure 15 shows the principle. figure 15. readout time of line is sum of row blanking time and on line readout time symbol name value a sync_y > 100 nsec b sync_y-clock_y > 50 nsec c clock_y-sync_y > 50 nsec d sync_x -clock_x > 50 ns notes 12. the applied clock_x, is filtered on chip to remove spikes. this is especially required at these high speeds. this filtering results in an on chip clock_x that is delayed in time with about 10 nsec. in other words, the data at the output has, with respect to the external clock_x, a propaga tion delay of 20 nsec. this 20 nsec come from 10 nsec of the generation of the internal clock_x and 10 nsec due to other on chip generated signals. 13. the analog signal will come out of the sensor with a 60/40 duty cycle. therefore, it is very important to have a very flexib le adc clock phase. this is necessary to fine-tune the adc to sample the analog signal at the correct moment. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 16 of 29 once the information of the selected line is stable the addressing of the pixels can start. this is done by means of a sync_x and a clock_x pulse in the same way as the y-addressing. the sync_x pulse downloads the address in the address register into the shift register and connects the first block of 16 columns to the 16 outputs. in fact on chip is a 32-output bus instead of 16, but on the rising edge of clock_x the first 16 columns of the bus are connected to the output stages. on the falling edge of clock_x, the last 16 columns of the selected bus are connected to the output stages. the timing of the x-shift register is comparable with the timing of the y-shift register, only that the timing is much faster. again the synchronization pulse must be high on the rising edge of clock_x. reduced row overhead time timing the row overhead time is the time between the selection of lines that one has to wait to get the data stable at the column ampli- fiers. this row overhead time is a loss in time, which should be reduced as much as possible. reduced timing a straightforward way of reducing the r.o.t is by using a sample and hold function. by means of sh_col the analog data is tracked during the first 200 nsec during the selection of a new set of lines. after 200 nsec, the analog data is stored. the rot is in this case reduced to 200 nsec, but as the internal data was not stable yet dynamic range is lost because not the complete analog levels are reached yet after 200 ns. figure 16 shows this principle. sh_col is now a pulse of 100 ns-200 ns starting 25 ns after norowsel. the duration of sh_col is equal to the rot. the shorter this time the shorter the rot will be however this lowers also the dynamic range. figure 16. reduced standard rot by means of sh_col signal. pre_col (short pulse), norowsel (short pulse), and sh_col (large pulse). [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 17 of 29 standard timing (rot = 200 ns figure 17. only pre_col and norowsel control signals are required. sh_col is made active low. in this case, the control signals norowsel and pre_col are made active for about 50 nsec from the moment the next line is selected. the time these pulses have to be active is related with the biasing resistance pre_load. the lower this resistance, the shorter the pulse duration of norowsel and pre_col may be. after these pulses are given, one has to wait for 180 nsec before the first pixels can be sampled. for this mode sh_col must be made active low. timing of serial parallel interface (spi) the serial parallel interface is used to upload the x- and y-address into the x- and y-address registers. this address is the starting point of the window of interest and is uploaded in the shift register by means of the corresponding synchronization pulse. the elementary unit cell of the serial to parallel interface is shown in figure 18 . 16 of these cells are connected in parallel, having a common load_addr and clock_spi form the entire uploadable address block. the uploaded addresses are applied to the sensor on the rising edge of signal load_addr. figure 18. schematic of spi the spi clock can have a frequency of 20 mhz and the data is l oaded into the register at the rising edge. the load_addr pulse s hould go high together or after the last falling edge of the spi_clock (see figure 18 ). the y-address has to be applied first and the x-address last. with respect to the timing in figure 18 , a1 corresponds with the least significant bit of the y-address (y0) and a16 corresponds with the most significant bit of the x- address (x5). the y-address is a 10 bit and the x-address is a 6-bit address register. d q c d q c address_in to address registers address_out clock_spi load_address 16 outputs to sensor : 6 x-address b its and 10 y-address bits clock_spi address unity cell entire uploadable address block load_addr a1 a2 a3 a16 load_addr clock_spi address command applied to sensor [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 18 of 29 if the x-address register is 6-bit wide this means that 64 values can be uploaded in this register. the x-start position however can only be adjusted with steps of 32 so only the 40 lsb's are accepted by the internal decod er (32 x 40=1280). the y-address register is 10 bit wide (1024 values), so the y-start address can be adjusted on a line by line basis. startup when starting the sensor the following sequence should be followed: 1. apply all power supplies. 2. upload spi register. 3. start driving/clocking of the sensor. make sure that the power supplies are completely stable before the spi is uploaded and the driv ing of the sensor can start. pin configuration the lupa-1300 sensor will be packed in a pga package with 145 pi ns. each bond pad consists of 2 pad openings, one for wafer probing and one for bonding. ta b l e 11 gives an overview of the pin names and their functionality. table 11. pin description of assembled lupa-1300 sensor in pga 144 package pin fp name function description b3 1 n.c. not connected c3 2 n.c. d3 3 voo supply 5v supply voltage output stages: 5v a2 4 gnd ground ground of the sensor b2 5 out1 analog out output 1 e3 6 voo supply 5v supply voltage output stages: 5v c2 7 out2 analog out output 2 d2 8 gnd ground ground of the sensor e2 9 out3 analog out output 3 a1 10 voo supply 5v supply voltage output stages: 5v f3 11 out4 analog out output 4 f2 12 gnd ground ground of the sensor b1 13 out5 analog out output 5 c1 14 voo supply 5v supply voltage output stages: 5v d1 15 out6 analog out output 6 g3 16 gnd ground ground of the sensor e1 17 out7 analog out output 7 g2 18 voo supply 5v supply voltage output stages: 5v f1 19 out8 analog out output 8 g1 20 gnd ground ground of the sensor h3 21 out9 analog out output 9 h2 22 voo supply 5v supply voltage output stages: 5v h1 23 out10 analog out output 10 j1 24 gnd ground ground of the sensor j2 25 out11 analog out output 11 j3 26 voo supply 5v supply voltage output stages: 5v k1 27 out12 analog out output 12 k2 28 gnd ground ground of the sensor l1 29 out13 analog out output 13 k3 30 voo supply 5v supply voltage output stages: 5v l2 31 out14 analog out output 14 [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 19 of 29 m1 32 gnd ground ground of the sensor n1 33 out15 analog out output 15 l3 34 voo supply 5v supply voltage output stages: 5v m2 35 out16 analog out output 16 p1 36 gnd ground ground of the sensor n2 37 voo supply 5v supply voltage output stages: 5v m3 38 n.c. p2 39 n.c. n3 40 gnd ground ground of the sensor n4 41 voo supply 5v supply voltage output stages: 5v n5 42 vstable supply 5v supply voltage to stabilize output stages: 5.5v p3 43 load_out biasing analog bias for output amplifiers 27 k to voo and capacitor of 100 nf to ground p5 44 dc_black testpin 6 dc-black signal required to characterize the output stages p4 45 vdd supply 5v supply voltage digital modules: 5v q1 46 gnd ground ground of the sensor n6 47 vdda supply 5v supply voltage analog modules: 5v p6 48 gnd ground ground of the sensor q2 49 vpix supply 4.5v supply voltage pixel array: 4.5v q3 50 eos_x digital i/o end of scan signal of the x-register: active high pulse indicates the end of the shift register is reached q4 51 nsf_load biasing analog bias for column stages: 100 k to vdda and capacitor of 100nf to ground n7 52 psf_load biasing analog bias for column stages: 240 k to gnd and capacitor of 100 nf to vdda p7 53 col_load biasing analog bias for column stages: 2 m to vdda and capacitor of 100 nf to ground q5 54 pre_load biasing analog bias for column stages: 10 k to vdda and capacitor of 100 nf to ground q6 55 n.c. q7 56 array_diode testpin 3 array of pixels as designed in pixel array n8 57 full_diode testpin 4 full diode with same array as array diode: 140 * 70 m 2 p8 58 temp_diode_p testpin 1 temperature diode p side q8 59 temp_diode_n testpin 2 temperature diode n side q9 60 n.c. p9 61 n.c. n9 62 n.c. q10 63 n.c. q11 64 n.c. q12 65 n.c. p10 66 n.c. n10 67 n.c. q13 68 n.c. p11 69 vpix supply 4.5v supply voltage pixel array: 4.5v table 11. pin description of assembled lupa-1300 sensor in pga 144 package (continued) pin fp name function description [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 20 of 29 p12 70 gnd ground ground of the sensor n11 71 vddr supply 5v supply voltage of the logic for the drivers: 5v n12 72 n.c. p13 73 vmem_l supply voltage supply for vmemory drivers: 3v- 5v (typ: 4.5v) n13 74 vmem_h supply voltage supply for vmemory drivers: 4v- 6v (typ. 6v) m13 75 vres_ds supply voltage supply for reset double sloped drivers: 4v - 5v q14 76 vres supply voltage supply for reset drivers: 5v - 6v (typ 6v) p14 77 gnd_res ground_ab ground anti-blooming: 0 - 1v l13 78 n.c. n14 79 n.c. m14 80 n.c. l14 81 n.c. q15 82 n.c. k13 83 n.c. k14 84 n.c. p15 85 n.c. n15 86 n.c. m15 87 n.c. j13 88 n.c. l15 89 n.c. j14 90 n.c. k15 91 n.c. j15 92 n.c. h13 93 n.c. h14 94 gnd ground ground for temperature module h15 95 temp testpin 5 dark level signal as function of temperature ( figure 7 ) g15 96 vdd supply supply voltage temperature module: 5v (has to be tunable to adjust output of temperatur e module to analog output) g14 97 n.c. g13 98 n.c. f15 99 n.c. f14 100 n.c. e15 101 reset_ds digital i/o double slope reset of the pixels: active high pulse f13 102 reset digital i/o reset signal of the pixels: active high pulse e14 103 mem_hl digital i/o control of vmemory signal: 5v: vmem_h, 0v: vmem_l d15 104 sample digital i/o samples the photodiode voltage onto the memory cell inside each pixel: active high pulse c15 105 precharge digital i/o precharge the memory cell inside the pixel: active high pulse e13 106 eos_y digital i/o end of scan signal of the y-register: active high pulse indicates the end of the shift register is reached d14 107 gnd_res ground_ab ground for the rese t drivers. can be used as anti-blooming by applying 1v instead of 0v b15 108 vres supply voltage supply for reset drivers: 5v - 6v (typ: 6v) c14 109 vres_ds supply voltage supply for reset double sloped drivers: 4v - 5v table 11. pin description of assembled lupa-1300 sensor in pga 144 package (continued) pin fp name function description [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 21 of 29 d13 110 vmem_h supply voltage supply for vmemory drivers: 5v- 6v (typ: 6v) b14 111 vmem_l supply voltage supply for vmemory drivers: 3v- 5v (typ: 4.5v) c13 112 vddr supply 5v supply voltage of the logic for the drivers: 5v c12 113 vpix supply 4.5v supply voltage pixel array: 4.5v c11 114 vdd supply 5v supply voltage digital modules: 5v b13 115 gnd ground ground of the sensor b11 116 n.c. b12 117 n.c. a15 118 n.c. c10 119 n.c. b10 120 n.c. a14 121 n.c. a13 122 n.c. a12 123 n.c. c9 124 n.c. b9 125 n.c. a11 126 load_addr digital i/o loads the address into the serial parallel interface (spi) a10 127 address digital i/o serial address to be downloaded into the spi a9 128 clock_spi digital i/o clock for the spi c8 129 decy_load digital i/o bia s for y address register: 27k to ground and capacitor of 100 nf to vdd b8 130 sync_y digital i/o syn chronisation of y-addre ss register: active high a8 131 clock_y digital i/o c lock of y-address register a7 132 norow_sel digital i/o control signal for norow_sel mode to reduce row blanking time: active low b7 133 sh_col digital i/o control signal for sh_col mode to reduce row blanking time: active low (baseline method): active low c7 134 pre_col digital i/o additional control signal for reducing the row blanking time a6 135 sync_x digital i/o synchronisation of the x-address register: active high a5 136 clock_x digital i/o clock of the x-address register a4 137 decx_load biasing bias for x address register: 27 k to ground and capacitor of 100 nf to vdd b6 138 black digital i/o controls black test function of the output stages: active high, connect to ground if not used c6 139 sel_active digital i/o set the output stag es active or in standby mode: active low a3 140 vdd supply 5v supply voltage digital modules: 5v b5 141 gnd ground ground of the sensor b4 142 vdda supply 5v supply voltage analog modules: 5v c5 143 gnd ground ground of the sensor c4 144 voo voo supply voltage output stages: 5v table 11. pin description of assembled lupa-1300 sensor in pga 144 package (continued) pin fp name function description [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 22 of 29 pad positioning and packaging package figure 19. package drawing of lupa-1300 sensor a b c d e f g h j k l m n p q 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 25,62 1 9,5 40,01 40,01 r 1 ,27 b d etail b scale 4/1 r 1 ,27 0,90 0,90 c d etail c scale 4/1 23,5 0,25 1 ,02 0,51 2,80 sectio na -a ' a a' 2,54 35,56 not e 1 ~ not e: 1 . die attach area should be m etallizedand connected to pad num ber d 4 all dim ensions in m m ? 1 ,78 29,62 1 ,27 4,57 0,20 4x0,5 r 1 1 7,5 23,62 [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 23 of 29 package and die figure 20. package drawing with die of lupa-1300 sensor the center of the pixel array is located 200 m to the right and 51 m above the center of the package. the first pixel is located at 9160 m to the left and 7219 to the bottom from this center. all distances are with a deviation of 50 m. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 24 of 29 color filter an optional color filter can be processed as well. the lupa-1300 can also be processed with a bayer rgb color pattern. pixel (0 ,0) has a red filter. figure 21. color filter arrangement on pixels glass transmittance monochrome a d263 glass will be used as protection glass lid on top of the lupa-1300 monochrome sensors. figure 22 shows the transmission characteristics of the d263 glass. figure 22. transmission characteristics of d263 glass used as protective cover for lupa-1300 sensors 0 10 20 30 40 50 60 70 80 90 10 0 400 500 600 700 800 900 wavelength [nm] transmission [%] [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 25 of 29 color for color devices a near infrared attenuating color filter glass is used. the dominant wavelength is around 490 nm. figure 23 shows the transmittance curve for the glass. a s8612 glass will be used as nir cut-off filter on top of the lupa-1300-c color image sensor. figure 24 shows the trans- mission characteristics of the s8612 glass. figure 23. transmission characteristics of s8612 glass used as nir cut-off filter handling and storage precautions handling precautions special care should be given when soldering image sensors with color filter arrays (rgb color filt ers), onto a circuit board, since color filters are sensitive to high temperatures. prolonged heating at elevated temperatures may result in deterioration of the performance of the sensor. the following recommendations are made to ensure that sensor performance is not compromised during end-users' assembly processes. board assembly device placement onto boards should be done in accordance with strict esd controls for class 0, jesd22 human body model, and class a, jesd22 machin e model device s. assembly operators should always wear all designated and approved grounding equipment; grounded wr ist straps at esd protected workstations are recommended including the use of ionized blowers. all tools should be esd protected. manual soldering when a soldering iron is used the following conditions should be observed: use a soldering iron with temperature control at the tip. the soldering iron tip temperature should not exceed 350c. the soldering period for each pin should be less than 5 seconds. precautions and cleaning avoid spilling solder flux on the cover glass; bare glass and particularly glass with antireflection filters may be adversely affected by the flux. avoid mechanical or particulate damage to the cover glass. it is recommended that isopropyl alcohol (ipa) be used as a solvent for cleaning the image sensor glass lid. when using other solvents, it should be confirme d beforehand whether the solvent will dissolve the package and/or the glass lid or not. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 26 of 29 storage conditions ordering information application notes and faqs q: can the lupa-1300 directly drive an adc? a: yes, coupling the lupa-1300 to a set of 16 adc's close to the chip is the preferred way of ope ration. a suitable adc must have thus input range equal or larger than the 1.2 v- 0 v sensor signal swing in view of the lupa-1300's s/n 10 bits are suitable. 11 or 12 bits may be considered too. input capacitance 20 pf or lower (high output loads will limit the speed). and no significant resistive loading. sampling frequency 40 mhz (or the application specific sample rate) the adc's input bandwidth must be sufficiently higher than the sampling frequency, in order to avoid rc contamination between successive pixels. description minimum maximum units conditions temperature ?10 66 c at 15% rh temperature ?10 38 c at 86% rh marketing part number description package cyil1sm1300aa-gdc mono with glass 145-pin pga cyil1sm1300aa-gwc mono without glass note 14. rh = relative humidity. [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 27 of 29 q: how does the dual slope extended dynamic range mode works? a: figure 24. dual slope diagram the green lines are the analog signal on the photodiode, which decrease as a result of exposure. the slope is determined by the amount of light at each pixel (the more light the steeper the slope). when the pi xels reach the saturation level the analog sig nal will not change despite further exposure. as you can see without any double slope pulse pixels p3 and p4 will reach saturation befor e the sample moment of the analog values, no signal will be acquir ed without double slope. when double slope is enabled a second rese t pulse will be given (blue line) at a certain time before the end of the integration time. this double slope reset pulse resets the analog signal of the pixels below this level to the reset level. after the reset the analog signal starts to decrease with the same sl ope as before the double slope reset pulse. if the double slope reset pu lse is placed at the end of the integration time (90% for inst ance) the analog signal that would have reach the saturation levels aren't saturated anymore (this increases the optical dynamic range) a t read out. it's important to notice that pixel signals above the double slope reset level will not be influenced by this double slope reset pulse (p1 and p2). look at the website to find pictur es taken with double slope mode on: http://www.fillfactory.be/htm/te chnology/htm/dual-slope.htm. p4 p3 p2 p1 reset level 1 reset level 2 saturation level total integration time reset double slope reset read double slope reset time (usually 5-10% of the total integration time) [+] feedback
cyil1sm1300aa document number: 38-05711 rev. *d page 28 of 29 appendix a: lupa- 1300 evaluation kit for evaluating purposes a lupa-1300 evaluation kit is available. the lupa-1300 evaluation kit consists of a multifunctional digital board (memory, seq uencer and ieee 1394 fire wire interface), an adc-board and an analog image sensor board. visual basic software (under win 2000 or xp) allows the grabbing and display of images and movies from the sensor. all acquired images and movies can be stored in different file formats (8- or 16-bit). all setting can be adjusted on the fly to evaluate th e sensors specifications. default r egister values can be loaded to start the software in a desired state. contact fillfactory (info@fillfactory.com) for more information on the evaluation kit. [+] feedback
document number: 38-05711 rev. *d revised september 21, 2009 page 29 of 29 purchase of i2c components from cypress or one of its sublic ensed associated companies conveys a license under the philips i2c patent rights to use these components in an i2c system, provided that the system conforms to the i2c standard specification as defi ned by philips. as from october 1st, 2006 philips semiconduct ors has a new trade name - nxp semiconductors. all products and company names mentioned in this document may be the trademarks of their respective holders. cyil1sm1300aa ? cypress semiconductor corporation, 2006-2009. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page document title: cyil1sm1300aa lupa-1300 1.3 mpxl high speed cmos image sensor document number: 38-05711 rev. ecn issue date orig. of change description of change ** 310396 see ecn sil initial cypress release. *a 370756 see ecn fpw additional timing specifications and removal of inconsistencies throughout the data sheet. *b 497127 see ecn qgs converted to frame file. *c 649105 see ecn fpw updated ordering information. *d 2766920 09/21/2009 nvea update ordering information and template. add part number to title. [+] feedback

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